PLL-Assisted Timing Circuit for Accurate TSV Leakage Binning

Shi-Yu Huang, Li-Ren Huang. PLL-Assisted Timing Circuit for Accurate TSV Leakage Binning. IEEE Design & Test of Computers, 31(4):36-42, 2014. [doi]

Authors

Shi-Yu Huang

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Li-Ren Huang

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