Shi-Yu Huang, Li-Ren Huang. PLL-Assisted Timing Circuit for Accurate TSV Leakage Binning. IEEE Design & Test of Computers, 31(4):36-42, 2014. [doi]
@article{HuangH14-11,
title = {PLL-Assisted Timing Circuit for Accurate TSV Leakage Binning},
author = {Shi-Yu Huang and Li-Ren Huang},
year = {2014},
doi = {10.1109/MDAT.2014.2335152},
url = {http://dx.doi.org/10.1109/MDAT.2014.2335152},
researchr = {https://researchr.org/publication/HuangH14-11},
cites = {0},
citedby = {0},
journal = {IEEE Design & Test of Computers},
volume = {31},
number = {4},
pages = {36-42},
}