The following publications are possibly variants of this publication:
- Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architectureYu-Ju Hong, Ya-Shih Huang, Juinn-Dar Huang. aspdac 2009: 19-24 [doi]
- A multicycle communication architecture and synthesis flow for Global interconnect Resource SharingWei-Sheng Huang, Yu-Ru Hong, Juinn-Dar Huang, Ya-Shih Huang. aspdac 2008: 16-21 [doi]
- A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle CommunicationChia-I Chen, Juinn-Dar Huang. ieicet, 93-A(7):1300-1308, 2010. [doi]
- CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architectureChia-I Chen, Juinn-Dar Huang. aspdac 2009: 67-72 [doi]
- Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File MicroarchitectureJuinn-Dar Huang, Chia-I Chen, Yen-Ting Lin, Wan-Ling Hsu. ieicet, 94-A(4):1151-1155, 2011. [doi]