Design Optimization of MV-NMOS for ESD Self-protection in 28nm CMOS technology

Kyong Jin Hwang, Sagar Premnath Karalkar, Vishal Ganesan, Sevashanmugam Marimuthu, Alban Zaka, Tom Herrmann, Bhoopendra Singh, Robert Gauthier. Design Optimization of MV-NMOS for ESD Self-protection in 28nm CMOS technology. In 2020 IEEE International Reliability Physics Symposium, IRPS 2020, Dallas, TX, USA, April 28 - May 30, 2020. pages 1-4, IEEE, 2020. [doi]

@inproceedings{HwangKGMZHSG20,
  title = {Design Optimization of MV-NMOS for ESD Self-protection in 28nm CMOS technology},
  author = {Kyong Jin Hwang and Sagar Premnath Karalkar and Vishal Ganesan and Sevashanmugam Marimuthu and Alban Zaka and Tom Herrmann and Bhoopendra Singh and Robert Gauthier},
  year = {2020},
  doi = {10.1109/IRPS45951.2020.9129515},
  url = {https://doi.org/10.1109/IRPS45951.2020.9129515},
  researchr = {https://researchr.org/publication/HwangKGMZHSG20},
  cites = {0},
  citedby = {0},
  pages = {1-4},
  booktitle = {2020 IEEE International Reliability Physics Symposium, IRPS 2020, Dallas, TX, USA, April 28 - May 30, 2020},
  publisher = {IEEE},
  isbn = {978-1-7281-3199-3},
}