Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada. Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells. In 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA. pages 377-380, IEEE Computer Society, 2004. [doi]
@inproceedings{IizukaIA04:0,
title = {Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells},
author = {Tetsuya Iizuka and Makoto Ikeda and Kunihiro Asada},
year = {2004},
url = {http://csdl.computer.org/comp/proceedings/isqed/2004/2093/00/20930377abs.htm},
tags = {layout, logic},
researchr = {https://researchr.org/publication/IizukaIA04%3A0},
cites = {0},
citedby = {0},
pages = {377-380},
booktitle = {5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA},
publisher = {IEEE Computer Society},
isbn = {0-7695-2093-6},
}