Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada. Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells. In 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA. pages 377-380, IEEE Computer Society, 2004. [doi]
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