Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells - researchr publication related

researchr

You are not signed in
Sign in
Sign up

Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada. Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells. In 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA. pages 377-380, IEEE Computer Society, 2004. [doi]

The following publications are possibly variants of this publication:

Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault MinimizationTetsuya Iizuka, Makoto Ikeda, Kunihiro Asada. ieicet, 88-A(7):1957-1963, 2005. [doi]

High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiabilityTetsuya Iizuka, Makoto Ikeda, Kunihiro Asada. aspdac 2004: 149-154 [doi]

runs on WebDSL