Clock design of 300MHz 128-bit 2-way superscalar microprocessor

Fujio Ishihara, Christian Klinger, Ken-ichi Agawa. Clock design of 300MHz 128-bit 2-way superscalar microprocessor. In Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan. pages 647-652, ACM, 2000. [doi]

@inproceedings{IshiharaKA00,
  title = {Clock design of 300MHz 128-bit 2-way superscalar microprocessor},
  author = {Fujio Ishihara and Christian Klinger and Ken-ichi Agawa},
  year = {2000},
  doi = {10.1145/368434.368857},
  url = {http://doi.acm.org/10.1145/368434.368857},
  tags = {design},
  researchr = {https://researchr.org/publication/IshiharaKA00},
  cites = {0},
  citedby = {0},
  pages = {647-652},
  booktitle = {Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan},
  publisher = {ACM},
  isbn = {0-7803-5974-7},
}