Low-voltage limitations of memory-rich nano-scale CMOS LSIs - researchr publication authors

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Kiyoo Itoh, Masashi Horiguchi, Masanao Yamaoka. Low-voltage limitations of memory-rich nano-scale CMOS LSIs. In Doris Schmitt-Landsiedel, Tobias Noll, editors, 33rd European Solid-State Circuits Conference, ESSCIRC 2007, Munich, Germany, 11-13 September 2007. pages 68-75, IEEE, 2007. [doi]

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