The following publications are possibly variants of this publication:
- Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIsKiyoo Itoh. icecsys 2007: 1 [doi]
- Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIsKiyoo Itoh, Riichiro Takemura. icecsys 2007: 739-742 [doi]
- Variability-Conscious Circuit Designs for Low-Voltage Memory-Rich Nano-Scale CMOS LSIsKiyoo Itoh. patmos 2011: 255 [doi]
- Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designersKiyoo Itoh, Masanao Yamaoka, Takayuki Kawahara. glvlsi 2007: 529-533 [doi]
- Ultra-Low Voltage Nano-Scale MemoriesKiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka. Series on Integrated Circuits and Systems, Springer, 2007. [doi]
- Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIsAkira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya, Masashi Horiguchi. cicc 2011: 1-7 [doi]