Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul. Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder. IEEE Trans. on Circuits and Systems, 61-II(7):521-525, 2014. [doi]
@article{JaiswalCBP14,
title = {Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder},
author = {Manish Kumar Jaiswal and Ray C. C. Cheung and M. Balakrishnan and Kolin Paul},
year = {2014},
doi = {10.1109/TCSII.2014.2327314},
url = {http://dx.doi.org/10.1109/TCSII.2014.2327314},
researchr = {https://researchr.org/publication/JaiswalCBP14},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on Circuits and Systems},
volume = {61-II},
number = {7},
pages = {521-525},
}