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Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul. Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder. IEEE Trans. on Circuits and Systems, 61-II(7):521-525, 2014. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Configurable Architecture for Double/Two-Parallel Single Precision Floating Point DivisionManish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul. isvlsi 2014: 332-337 [doi] Dual-mode double precision / two-parallel single precision floating point multiplier architectureManish Kumar Jaiswal, Hayden Kwok-Hay So. vlsi 2015: 213-218 [doi] Architecture for Dual-Mode Quadruple Precision Floating Point AdderManish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So. isvlsi 2015: 249-254 [doi]
The following publications are possibly variants of this publication: