The following publications are possibly variants of this publication:
- Architecture for quadruple precision floating point division with multi-precision supportManish Kumar Jaiswal, Hayden Kwok-Hay So. asap 2016: 239-240 [doi]
- Taylor Series Based Architecture for Quadruple Precision Floating Point DivisionManish Kumar Jaiswal, Hayden Kwok-Hay So. isvlsi 2016: 518-523 [doi]
- Area-Efficient Architectures for Large Integer and Quadruple Precision Floating Point MultipliersManish Kumar Jaiswal, Ray C. C. Cheung. fccm 2012: 25-28 [doi]
- Configurable Architectures for Multi-Mode Floating Point AddersManish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So, M. Balakrishnan, Kolin Paul, Ray C. C. Cheung. tcas, 62-I(8):2079-2090, 2015. [doi]
- Unified Architecture for Double/Two-Parallel Single Precision Floating Point AdderManish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul. tcas, 61-II(7):521-525, 2014. [doi]
- Area-Efficient Architecture for Dual-Mode Double Precision Floating Point DivisionManish Kumar Jaiswal, Hayden Kwok-Hay So. tcas, 64-I(2):386-398, 2017. [doi]