FPGA-Efficient Hybrid LUT/CORDIC Architecture

Ireneusz Janiszewski, Hermann Meuth, Bernhard Hoppe. FPGA-Efficient Hybrid LUT/CORDIC Architecture. In Jürgen Becker, Marco Platzner, Serge Vernalde, editors, Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings. Volume 3203 of Lecture Notes in Computer Science, pages 933-937, Springer, 2004. [doi]

Authors

Ireneusz Janiszewski

This author has not been identified. Look up 'Ireneusz Janiszewski' in Google

Hermann Meuth

This author has not been identified. Look up 'Hermann Meuth' in Google

Bernhard Hoppe

This author has not been identified. Look up 'Bernhard Hoppe' in Google