The following publications are possibly variants of this publication:
- A High Performance Partially-Parallel Irregular LDPC Decoder Based on Sum-Delta Message Passing ScheduleWen Ji, Yuta Abe, Takeshi Ikenaga, Satoshi Goto. ieicet, 91-A(12):3622-3629, 2008. [doi]
- Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing AlgorithmKazunori Shimizu, Tatsuyuki Ishikawa, Takeshi Ikenaga, Satoshi Goto, Nozomu Togawa. iccd 2005: 503-510 [doi]
- Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing ScheduleKazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto. ieicet, 89-A(12):3602-3612, 2006. [doi]
- Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing ScheduleKazunori Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto. ieicet, 89-A(4):969-978, 2006. [doi]
- An efficient majority-logic based message-passing algorithm for non-binary LDPC decodingYichao Lu, Nanfan Qiu, Zhixiang Chen, Satoshi Goto. apccas 2012: 479-482 [doi]