Designing soft-error-aware circuits with power and speed optimization

H. Jiang, H. Zhang, Balaji Narasimham, Lloyd W. Massengill, Bharat L. Bhuva. Designing soft-error-aware circuits with power and speed optimization. In IEEE International Reliability Physics Symposium, IRPS 2018, Burlingame, CA, USA, March 11-15, 2018. pages 5-1, IEEE, 2018. [doi]

@inproceedings{JiangZNMB18,
  title = {Designing soft-error-aware circuits with power and speed optimization},
  author = {H. Jiang and H. Zhang and Balaji Narasimham and Lloyd W. Massengill and Bharat L. Bhuva},
  year = {2018},
  doi = {10.1109/IRPS.2018.8353692},
  url = {https://doi.org/10.1109/IRPS.2018.8353692},
  researchr = {https://researchr.org/publication/JiangZNMB18},
  cites = {0},
  citedby = {0},
  pages = {5},
  booktitle = {IEEE International Reliability Physics Symposium, IRPS 2018, Burlingame, CA, USA, March 11-15, 2018},
  publisher = {IEEE},
  isbn = {978-1-5386-5479-8},
}