Chip Substrate Resistance Modeling Technique for Integrated Circuit Design

Thomas A. Johnson, Ronald W. Knepper, Victor Marcello, Wen Wang. Chip Substrate Resistance Modeling Technique for Integrated Circuit Design. IEEE Trans. on CAD of Integrated Circuits and Systems, 3(2):126-134, 1984. [doi]

Authors

Thomas A. Johnson

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Ronald W. Knepper

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Victor Marcello

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Wen Wang

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