Thomas A. Johnson, Ronald W. Knepper, Victor Marcello, Wen Wang. Chip Substrate Resistance Modeling Technique for Integrated Circuit Design. IEEE Trans. on CAD of Integrated Circuits and Systems, 3(2):126-134, 1984. [doi]
@article{JohnsonKMW84,
title = {Chip Substrate Resistance Modeling Technique for Integrated Circuit Design},
author = {Thomas A. Johnson and Ronald W. Knepper and Victor Marcello and Wen Wang},
year = {1984},
url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=28428&arnumber=1270066&count=7&index=2},
tags = {modeling, design},
researchr = {https://researchr.org/publication/JohnsonKMW84},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {3},
number = {2},
pages = {126-134},
}