Andrew B. Kahng, Hyein Lee. Minimum implant area-aware gate sizing and placement. In Joseph R. Cavallaro, Tong Zhang 0002, Alex K. Jones, Hai Helen Li, editors, Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21 - 23, 2014. pages 57-62, ACM, 2014. [doi]
@inproceedings{KahngL14, title = {Minimum implant area-aware gate sizing and placement}, author = {Andrew B. Kahng and Hyein Lee}, year = {2014}, doi = {10.1145/2591513.2591542}, url = {http://doi.acm.org/10.1145/2591513.2591542}, researchr = {https://researchr.org/publication/KahngL14}, cites = {0}, citedby = {0}, pages = {57-62}, booktitle = {Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21 - 23, 2014}, editor = {Joseph R. Cavallaro and Tong Zhang 0002 and Alex K. Jones and Hai Helen Li}, publisher = {ACM}, isbn = {978-1-4503-2816-6}, }