Comparing Layouts with HDL Models: A Formal Verification Technique - researchr publication authors

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Timothy Kam, P. A. Subrahmanyam. Comparing Layouts with HDL Models: A Formal Verification Technique. In Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD 92, Cambridge, MA, USA, October 11-14, 1992. pages 588-591, IEEE Computer Society, 1992.

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