Comparing Layouts with HDL Models: A Formal Verification Technique

Timothy Kam, P. A. Subrahmanyam. Comparing Layouts with HDL Models: A Formal Verification Technique. In Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD 92, Cambridge, MA, USA, October 11-14, 1992. pages 588-591, IEEE Computer Society, 1992.

@inproceedings{KamS92,
  title = {Comparing Layouts with HDL Models: A Formal Verification Technique},
  author = {Timothy Kam and P. A. Subrahmanyam},
  year = {1992},
  tags = {layout},
  researchr = {https://researchr.org/publication/KamS92},
  cites = {0},
  citedby = {0},
  pages = {588-591},
  booktitle = {Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD  92, Cambridge, MA, USA, October 11-14, 1992},
  publisher = {IEEE Computer Society},
  isbn = {0-8186-3110-4},
}