Timothy Kam, P. A. Subrahmanyam. Comparing layouts with HDL models: a formal verification technique. IEEE Trans. on CAD of Integrated Circuits and Systems, 14(4):503-509, 1995. [doi]
@article{KamS95,
title = {Comparing layouts with HDL models: a formal verification technique},
author = {Timothy Kam and P. A. Subrahmanyam},
year = {1995},
doi = {10.1109/43.372376},
url = {http://doi.ieeecomputersociety.org/10.1109/43.372376},
tags = {layout},
researchr = {https://researchr.org/publication/KamS95},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {14},
number = {4},
pages = {503-509},
}