Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop - researchr publication authors

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Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy. Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop. In Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007. pages 934-939, IEEE, 2007. [doi]

This author has not been identified. Look up 'Kunhyuk Kang' in GoogleThis author has not been identified. Look up 'Kee-Jong Kim' in GoogleThis author has not been identified. Look up 'Kaushik Roy' in Google

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