Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop

Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy. Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop. In Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007. pages 934-939, IEEE, 2007. [doi]

@inproceedings{KangKR07,
  title = {Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop},
  author = {Kunhyuk Kang and Kee-Jong Kim and Kaushik Roy},
  year = {2007},
  doi = {10.1109/DAC.2007.375298},
  url = {http://doi.ieeecomputersociety.org/10.1109/DAC.2007.375298},
  tags = {design},
  researchr = {https://researchr.org/publication/KangKR07},
  cites = {0},
  citedby = {0},
  pages = {934-939},
  booktitle = {Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007},
  publisher = {IEEE},
}