Interconnect Estimation for FPGAs under Timing Driven Domains - researchr publication related

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PariVallal Kannan, Dinesh Bhatia. Interconnect Estimation for FPGAs under Timing Driven Domains. In 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings. pages 344-349, IEEE Computer Society, 2003. [doi]

The following publications are possibly variants of this publication:

Interconnect estimation for FPGAsP. Kannan, D. Bhatia. tcad, 25(8):1523-1534, 2006. [doi]

Timing Aware Interconnect Prediction Models for FPGAsShankar Balachandran, Dinesh Bhatia. fpl 2005: 167-172

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