A yield and speed enhancement scheme under within-die variations on 90nm LUT array

Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera. A yield and speed enhancement scheme under within-die variations on 90nm LUT array. In Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, CICC 2005, DoubleTree Hotel, San Jose, California, USA, September 18-21, 2005. pages 601-604, IEEE, 2005. [doi]

@inproceedings{KatsukiKKO05,
  title = {A yield and speed enhancement scheme under within-die variations on 90nm LUT array},
  author = {Kazuya Katsuki and Manabu Kotani and Kazutoshi Kobayashi and Hidetoshi Onodera},
  year = {2005},
  doi = {10.1109/CICC.2005.1568739},
  url = {http://dx.doi.org/10.1109/CICC.2005.1568739},
  researchr = {https://researchr.org/publication/KatsukiKKO05},
  cites = {0},
  citedby = {0},
  pages = {601-604},
  booktitle = {Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, CICC 2005, DoubleTree Hotel, San Jose, California, USA, September 18-21, 2005},
  publisher = {IEEE},
  isbn = {0-7803-9023-7},
}