A 6T SRAM cell based pipelined 2R/1W memory design using 28nm UTBB-FDSOI - researchr publication authors

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Ramandeep Kaur, Alexander Fell, Harsh Rawat. A 6T SRAM cell based pipelined 2R/1W memory design using 28nm UTBB-FDSOI. In 28th IEEE International System-on-Chip Conference, SOCC 2015, Beijing, China, September 8-11, 2015. pages 310-315, IEEE, 2015. [doi]

This author has not been identified. Look up 'Ramandeep Kaur' in GoogleThis author has not been identified. Look up 'Alexander Fell' in GoogleThis author has not been identified. Look up 'Harsh Rawat' in Google

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