Ramandeep Kaur, Alexander Fell, Harsh Rawat. A 6T SRAM cell based pipelined 2R/1W memory design using 28nm UTBB-FDSOI. In 28th IEEE International System-on-Chip Conference, SOCC 2015, Beijing, China, September 8-11, 2015. pages 310-315, IEEE, 2015. [doi]
@inproceedings{KaurFR15,
title = {A 6T SRAM cell based pipelined 2R/1W memory design using 28nm UTBB-FDSOI},
author = {Ramandeep Kaur and Alexander Fell and Harsh Rawat},
year = {2015},
doi = {10.1109/SOCC.2015.7406973},
url = {http://dx.doi.org/10.1109/SOCC.2015.7406973},
researchr = {https://researchr.org/publication/KaurFR15},
cites = {0},
citedby = {0},
pages = {310-315},
booktitle = {28th IEEE International System-on-Chip Conference, SOCC 2015, Beijing, China, September 8-11, 2015},
publisher = {IEEE},
isbn = {978-1-4673-9094-1},
}