Ramandeep Kaur, Alexander Fell, Harsh Rawat. A 6T SRAM cell based pipelined 2R/1W memory design using 28nm UTBB-FDSOI. In 28th IEEE International System-on-Chip Conference, SOCC 2015, Beijing, China, September 8-11, 2015. pages 310-315, IEEE, 2015. [doi]
Abstract is missing.