Peak power reduction of a sensor network processor fabricated with Deeply Depleted Channel transistors in 65nm technology - researchr publication authors

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Kentaro Kawakami, Takeshi Shiro, Hironobu Yamasaki, Katsuhiro Yoda, Hiroaki Fujimoto, Kenichi Kawasaki, Yasuhiro Watanabe. Peak power reduction of a sensor network processor fabricated with Deeply Depleted Channel transistors in 65nm technology. In International Symposium on Quality Electronic Design, ISQED 2013, Santa Clara, CA, USA, March 4-6, 2013. pages 422-429, IEEE, 2013. [doi]

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