Kentaro Kawakami, Takeshi Shiro, Hironobu Yamasaki, Katsuhiro Yoda, Hiroaki Fujimoto, Kenichi Kawasaki, Yasuhiro Watanabe. Peak power reduction of a sensor network processor fabricated with Deeply Depleted Channel transistors in 65nm technology. In International Symposium on Quality Electronic Design, ISQED 2013, Santa Clara, CA, USA, March 4-6, 2013. pages 422-429, IEEE, 2013. [doi]
@inproceedings{KawakamiSYYFKW13,
title = {Peak power reduction of a sensor network processor fabricated with Deeply Depleted Channel transistors in 65nm technology},
author = {Kentaro Kawakami and Takeshi Shiro and Hironobu Yamasaki and Katsuhiro Yoda and Hiroaki Fujimoto and Kenichi Kawasaki and Yasuhiro Watanabe},
year = {2013},
doi = {10.1109/ISQED.2013.6523646},
url = {http://dx.doi.org/10.1109/ISQED.2013.6523646},
researchr = {https://researchr.org/publication/KawakamiSYYFKW13},
cites = {0},
citedby = {0},
pages = {422-429},
booktitle = {International Symposium on Quality Electronic Design, ISQED 2013, Santa Clara, CA, USA, March 4-6, 2013},
publisher = {IEEE},
isbn = {978-1-4673-4951-2},
}