Path-delay-fault testable nonscan sequential circuits

Wuudiann Ke, Premachandran R. Menon. Path-delay-fault testable nonscan sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems, 14(5):576-582, 1995. [doi]

@article{KeM95:1,
  title = {Path-delay-fault testable nonscan sequential circuits},
  author = {Wuudiann Ke and Premachandran R. Menon},
  year = {1995},
  doi = {10.1109/43.384419},
  url = {http://doi.ieeecomputersociety.org/10.1109/43.384419},
  tags = {testing},
  researchr = {https://researchr.org/publication/KeM95%3A1},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
  volume = {14},
  number = {5},
  pages = {576-582},
}