The following publications are possibly variants of this publication:
- A third-order /spl Sigma//spl Delta/ modulator in 0.18-/spl mu/m CMOS with calibrated mixed-mode integratorsJae Hoon Shim, In-Cheol Park, Beomsup Kim. jssc, 40(4):918-925, 2005. [doi]
- A 0.18-/spl mu/m CMOS front-end processor for a Blu-Ray Disc recorder with an adaptive PRMLGoang-seog Choi, Joo Seon Kim, Hyun Jeong Park, Young Jun Ahn, Hyun Soo Park, Jum-Han Bae, In-Sik Park, Dong-Ho Shin. jssc, 40(1):342-350, 2005. [doi]
- A unified turbo/Viterbi channel decoder for 3GPP mobile wireless in 0.18-/spl mu/m CMOSMark A. Bickerstaff, David Garrett, Tom Prokop, Charles Thomas 0002, Benjamin Widdup, Gongyu Zhou, Linda M. Davis, Graeme Woodward, Chris Nicol, Ran-Hong Yan. jssc, 37(11):1555-1564, 2002. [doi]
- Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-/spl mu/m CMOSKen Mai, Ron Ho, Elad Alon, Dean Liu, Younggon Kim, Dinesh Patil, Mark A. Horowitz. jssc, 40(1):261-275, 2005. [doi]