A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm - researchr publication authors

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Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Yukihito Oowaki. A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm. In IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010. pages 326-327, IEEE, 2010. [doi]

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