Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator

Wooseok Kim, Jaejin Park, Hojin Park, Deog Kyoon Jeong. Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator. J. Solid-State Circuits, 49(3):657-672, 2014. [doi]

Authors

Wooseok Kim

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Jaejin Park

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Hojin Park

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Deog Kyoon Jeong

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