Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator

Wooseok Kim, Jaejin Park, Hojin Park, Deog Kyoon Jeong. Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator. J. Solid-State Circuits, 49(3):657-672, 2014. [doi]

References

No references recorded for this publication.

Cited by

No citations of this publication recorded.