Wooseok Kim, Jaejin Park, Hojin Park, Deog Kyoon Jeong. Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator. J. Solid-State Circuits, 49(3):657-672, 2014. [doi]
@article{KimPPJ14,
title = {Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator},
author = {Wooseok Kim and Jaejin Park and Hojin Park and Deog Kyoon Jeong},
year = {2014},
doi = {10.1109/JSSC.2014.2298455},
url = {http://dx.doi.org/10.1109/JSSC.2014.2298455},
researchr = {https://researchr.org/publication/KimPPJ14},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {49},
number = {3},
pages = {657-672},
}