Seyoung Kim, Seungho Yang, Hyein Lim, Hyein Lee, Jongwook Jeon, Jung Yun Choi, Jaeha Kim. Accurate Layout-Dependent Effect Model in 10 nm-Class DRAM Process Using Area-Efficient Array Test Circuits. IEEE Access, 11:70691-70697, 2023. [doi]
Abstract is missing.