Keiji Kishine, Kyoko Fujimoto, Satomi Kusanagi, Haruhiko Ichino. PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits. J. Solid-State Circuits, 39(5):740-750, 2004. [doi]
@article{KishineFKI04,
title = {PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits},
author = {Keiji Kishine and Kyoko Fujimoto and Satomi Kusanagi and Haruhiko Ichino},
year = {2004},
doi = {10.1109/JSSC.2004.826319},
url = {https://doi.org/10.1109/JSSC.2004.826319},
researchr = {https://researchr.org/publication/KishineFKI04},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {39},
number = {5},
pages = {740-750},
}