Haruhiko Ichino - researchr alias

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Viewing Publication 1 - 17 from 17

2007

MAC protocol based on cross-layer design methodology for fast link in wireless communication systemsShoko Ohteru, Keiji Kishine, Haruhiko Ichino. ieiceee, 4(19):593-599, 2007. [doi]

2005

Physical Layer OAM&P Signaling Method for 10 Gbit/s Ethernet Transport over Optical NetworksKazuhiko Terada, Kenji Kawai, Osamu Ishida, Keiji Kishine, Noboru Iwasaki, Haruhiko Ichino. ieicet, 88-B(10):3952-3961, 2005. [doi]

2004

PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuitsKeiji Kishine, Kyoko Fujimoto, Satomi Kusanagi, Haruhiko Ichino. jssc, 39(5):740-750, 2004. [doi]

2002

Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUXKeiji Kishine, Kiyoshi Ishii, Haruhiko Ichino. jssc, 37(1):38-50, 2002. [doi]

2000

A jitter suppression technique for a 2.48832 Gb/s clock and data recovery circuitKiyoshi Ishii, Keiji Kishine, Haruhiko Ichino. iscas 2000: 261-264 [doi]

A 0.6-W 10-Gb/s SONET/SDH bit-error-rate monitoring LSIKenji Kawai, Haruhiko Ichino. jssc, 35(12):1988-1991, 2000. [doi]

1999

A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI designKenji Kawai, Keiichi Koike, Yuichiro Takei, Akira Onozawa, Hitoshi Obara, Haruhiko Ichino. jssc, 34(1):12-17, 1999. [doi]

A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANsKeiji Kishine, Noboru Ishihara, Ken-ichi Takiguchi, Haruhiko Ichino. jssc, 34(6):805-812, 1999. [doi]

1998

High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processingKeiichi Koike, Kenji Kawai, Akira Onozawa, Yuichiro Takei, Yoshiji Kobayashi, Haruhiko Ichino. jssc, 33(10):1536-1544, 1998. [doi]

1997

A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logicKeiji Kishine, Yoshiji Kobayashi, Haruhiko Ichino. jssc, 32(2):215-221, 1997. [doi]

1995

Very-high-speed Si bipolar static frequency dividers with new T-type flip-flopsKiyoshi Ishii, Haruhiko Ichino, Minoru Togashi, Yoshiji Kobayashi, Chikara Yamaguchi. jssc, 30(1):19-24, January 1995. [doi]

1994

Maximum operating frequency in Si bipolar master-slave toggle flip-flop circuitKiyoshi Ishii, Haruhiko Ichino, Chikara Yamaguchi. jssc, 29(7):754-760, July 1994. [doi]

High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technologyKiyoshi Ishii, Haruhiko Ichino, Member, ZEEE, Yoshiji Kobayashi, Chikara Yamaguchi. jssc, 29(5):546-550, May 1994. [doi]

1993

20 Gb/s digital SSIs using AlGaAs/GaAs heterojunction bipolar transistors for future optical transmission systemsHaruhiko Ichino. jssc, 28(2):115-122, February 1993. [doi]

1991

Comments on '18-GHz 1/8 dynamic frequency divider using Si bipolar technologies (and reply)Rainer H. Derksen, Haruhiko Ichino. jssc, 26(8):1176, August 1991. [doi]

1990

12-Gb/s decision circuit IC using AlGaAs/GaAS HBT technologyHaruhiko Ichino, Noboru Ishihara, Yoshiki Yamauchi, Osaake Nakajima, Koichi Nagata, Takumi Nittono. jssc, 25(6):1538-1543, December 1990. [doi]

1989

18-GHz 1/8 dynamic frequency divider using Si bipolar technologiesHaruhiko Ichino, Noboru Ishihara, Masao Suzuki, Shinsuke Konaka. jssc, 24(6):1723-1728, December 1989. [doi]

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