PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits - researchr publication

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Keiji Kishine, Kyoko Fujimoto, Satomi Kusanagi, Haruhiko Ichino. PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits. J. Solid-State Circuits, 39(5):740-750, 2004. [doi]

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