Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control

Keiji Kishine, Hiromi Inaba, Yusuke Ohtomo, Makoto Nakamura, Mitsuo Nakamura. Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control. In 55th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2012, Boise, ID, USA, August 5-8, 2012. pages 602-605, IEEE, 2012. [doi]

Authors

Keiji Kishine

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Hiromi Inaba

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Yusuke Ohtomo

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Makoto Nakamura

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Mitsuo Nakamura

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