Keiji Kishine, Hiromi Inaba, Yusuke Ohtomo, Makoto Nakamura, Mitsuo Nakamura. Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control. In 55th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2012, Boise, ID, USA, August 5-8, 2012. pages 602-605, IEEE, 2012. [doi]
@inproceedings{KishineIONN12, title = {Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control}, author = {Keiji Kishine and Hiromi Inaba and Yusuke Ohtomo and Makoto Nakamura and Mitsuo Nakamura}, year = {2012}, doi = {10.1109/MWSCAS.2012.6292092}, url = {https://doi.org/10.1109/MWSCAS.2012.6292092}, researchr = {https://researchr.org/publication/KishineIONN12}, cites = {0}, citedby = {0}, pages = {602-605}, booktitle = {55th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2012, Boise, ID, USA, August 5-8, 2012}, publisher = {IEEE}, isbn = {978-1-4673-2526-4}, }