Design procedure of 25.8 Gbps/lane re-timer IC regarding power integrity

Kenji Kogo, Takayasu Norimatsu, Norihiro Kohmu, Takashi Kawamoto. Design procedure of 25.8 Gbps/lane re-timer IC regarding power integrity. IEICE Electronic Express, 14(23):20171017, 2017. [doi]

Authors

Kenji Kogo

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Takayasu Norimatsu

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Norihiro Kohmu

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Takashi Kawamoto

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