Design procedure of 25.8 Gbps/lane re-timer IC regarding power integrity

Kenji Kogo, Takayasu Norimatsu, Norihiro Kohmu, Takashi Kawamoto. Design procedure of 25.8 Gbps/lane re-timer IC regarding power integrity. IEICE Electronic Express, 14(23):20171017, 2017. [doi]

Abstract

Abstract is missing.