Tetsushi Koide, Shin ichi Wakabayashi, Noriyoshi Yoshida. Pin assignment with global routing for VLSI building block layout. IEEE Trans. on CAD of Integrated Circuits and Systems, 15(12):1575-1583, 1996. [doi]
@article{KoideWY96,
title = {Pin assignment with global routing for VLSI building block layout},
author = {Tetsushi Koide and Shin ichi Wakabayashi and Noriyoshi Yoshida},
year = {1996},
doi = {10.1109/43.552091},
url = {http://doi.ieeecomputersociety.org/10.1109/43.552091},
tags = {layout, routing},
researchr = {https://researchr.org/publication/KoideWY96},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {15},
number = {12},
pages = {1575-1583},
}