Carrier-Scale Packet Processing Architecture Using Interleaved 3D-Stacked DRAM and Its Analysis - researchr publication authors

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Tomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki. Carrier-Scale Packet Processing Architecture Using Interleaved 3D-Stacked DRAM and Its Analysis. IEEE Access, 7:75500-75514, 2019. [doi]

This author has not been identified. Look up 'Tomohiro Korikawa' in GoogleThis author has not been identified. Look up 'Akio Kawabata' in GoogleThis author has not been identified. Look up 'Fujun He' in GoogleThis author has not been identified. Look up 'Eiji Oki' in Google

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