The following publications are possibly variants of this publication:
- Carrier-Scale Packet Processing System Using Interleaved 3D-Stacked DRAMTomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki. icc 2018: 1-6 [doi]
- Packet Processing Architecture With Off-Chip LLC Using Interleaved 3D-Stacked DRAMTomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki. hpsr 2019: 1-6 [doi]
- Packet Processing Architecture with Off-Chip Last Level Cache Using Interleaved 3D-Stacked DRAMTomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki. ieicetb, 104-B(2):149-157, 2021. [doi]
- Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAMTomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki. access, 8:59290-59304, 2020. [doi]