Vyas Krishnan, Srinivas Katkoori. Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis. In 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India. pages 641-646, IEEE Computer Society, 2008. [doi]
@inproceedings{KrishnanK08,
title = {Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis},
author = {Vyas Krishnan and Srinivas Katkoori},
year = {2008},
doi = {10.1109/VLSI.2008.85},
url = {http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.85},
tags = {rule-based},
researchr = {https://researchr.org/publication/KrishnanK08},
cites = {0},
citedby = {0},
pages = {641-646},
booktitle = {21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India},
publisher = {IEEE Computer Society},
}