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A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism

Hajime Kubosawa, Naoshi Higaki, Satoshi Ando, Hiromasa Takahashi, Yoshimi Asada, Hideaki Anbutsu, Tomio Sato, Masato Sakate, Atsuhiro Suga, Michihide Kimura, Hideo Miyake, Hiroshi Okano, Akira Asato, Yasunori Kimura, Hiroshi Nakayama, Masayoshi Kimoto, Katsuji Hirochi, Hideki Saito 0005, Norio Kaido, Yukihiro Nakagawa, Toshio Shimada. A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism. J. Solid-State Circuits, 34(11):1619-1626, 1999. [doi]

Authors

Hajime Kubosawa

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Naoshi Higaki

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Satoshi Ando

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Hiromasa Takahashi

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Yoshimi Asada

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Hideaki Anbutsu

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Tomio Sato

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Masato Sakate

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Atsuhiro Suga

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Michihide Kimura

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Hideo Miyake

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Hiroshi Okano

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Akira Asato

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Yasunori Kimura

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Hiroshi Nakayama

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Masayoshi Kimoto

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Katsuji Hirochi

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Hideki Saito 0005

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Norio Kaido

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Yukihiro Nakagawa

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Toshio Shimada

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